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[VHDL-FPGA-Verilog] MCU_FPGA_Interface

Description: msp430单片机用IO口模拟总线时序，与FPGA进行交互的程序，附源代码，verilog，有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.
Platform: | Size: 870400 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源-Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has been testing, it is a good resource
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] UARTReceiver

Description: serial communication using uart FPGA-based embedded system
Platform: | Size: 1024 | Author: hazwaj | Hits:

[VHDL-FPGA-Verilog] uart_niosII

Description: 基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
Platform: | Size: 348160 | Author: 陈涛 | Hits:

[Other] 430_FPGA

Description: 可很好完成MSP430与FPGA的并行通信，-May very well complete the MSP430 parallel with the FPGA communication,
Platform: | Size: 3072 | Author: 我有我自我 | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL_CODE

Description: altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
Platform: | Size: 32768 | Author: 张东 | Hits:

[VHDL-FPGA-Verilog] my_uart_module

Description: use this source code interfacing fpga with serial UART
Platform: | Size: 4096 | Author: Harry Sunaryo | Hits:

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 串口FPGA实现，采用了状态机的方案 串口FPGA实现，采用了状态机的方案-FPGA UART
Platform: | Size: 4096 | Author: robincyh | Hits:

[VHDL-FPGA-Verilog] uart

Description: the uart model is used to design the synthies and beherival model in verilog fpga
Platform: | Size: 1024 | Author: dhanagopal | Hits:

[VHDL-FPGA-Verilog] UART_Verilog

Description: Altera FPGA的UART通讯程序-Altera FPGA' s UART communication program
Platform: | Size: 495616 | Author: bobpark | Hits:

[VHDL-FPGA-Verilog] x3cs400_uart

Description: 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
Platform: | Size: 569344 | Author: lingfeng | Hits:

[Software Engineering] FPGA_RS232

Description: 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction.
Platform: | Size: 215040 | Author: jalon | Hits:

[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte

Description: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Platform: | Size: 5072896 | Author: mabeibei | Hits:

[VHDL-FPGA-Verilog] uart1

Description: RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
Platform: | Size: 237568 | Author: 徐 | Hits:

[Other] UART

Description: 这是用VHDL语言编写的FPGA串口程序，希望对大家有用。-It is written in VHDL, FPGA serial program, we want to be useful.
Platform: | Size: 16384 | Author: 刘金鑫 | Hits:

[Documents] uart

Description: this is a code for uart implementation........... this can be implimented on a fpga board-this is a code for uart implementation........... this can be implimented on a fpga board........
Platform: | Size: 2048 | Author: asdfg | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用VHDL编程，在FPGA上实现串口的控制！希望一切分享一下！-Using VHDL programming, the FPGA, Serial control! Hope that all share!
Platform: | Size: 2665472 | Author: ncf | Hits:

[Com Port] RS232

Description: simple example for uart on fpga
Platform: | Size: 714752 | Author: Jay | Hits:

[VHDL-FPGA-Verilog] hello_world

Description: FPGA SOPC设计的uart串口 NIOS II中的程序 自己亲自做的 在串口调试工具中成功调试-FOGA SOPC UART NIOS II
Platform: | Size: 2048 | Author: 宋冬锋 | Hits:
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